Electronic systems can typically include a data storage capability. For example, bi-stable circuits, such as flip-flops can maintain a data value in one of two binary logic values depending upon an input to the flip-flop. One commonly used bi-stable circuit that can maintain a logic value until another value is written or rewritten is a latch.
A latch can take a number of different forms. For example, a latch can include cross-coupled inverters that can latch a data value on complementary data nodes until a new data value is rewritten. Such latches are often used as static random access memory (SRAM) cells. An SRAM type latch can store true and complementary logic values sent to the latch from, as but one example, a data bus. Such stored data values can be read when an execution unit fetches (e.g. reads) data from an addressed storage cell.
Unlike memory cells that can require periodic refresh (i.e., dynamic random access memory (DRAM) cells), an SRAM type latch can retain stored data without requiring refresh until such a time as power is removed from the latch. However, there are many applications in which it is desirable for a data value to be retained even in the absence of power. As but one example, in some systems read-only-memory (ROM) storage media can be used to store software in applications that do not readily change or are needed as a boot-up driver. Even more particularly, a ROM is often used as part of a basic input/output system (BIOS) code, and can be used in look-up tables and character generators.
Once programmed, how a ROM can maintains a programmed state can vary according to the type of ROM used. Generally speaking, a ROM can utilize a non-volatile storage element. As is well known, a non-volatile storage element can maintain a stored logic value after power is removed from the circuit. Conversely, a volatile storage element will lose a stored data value once power is removed.
Latch circuits are typically understood to be volatile circuits. On the other hand, masked ROMs or field programmable ROMs (PROMs) are a form of nonvolatile memory. Other types of nonvolatile memories include electrically programmable ROMs (EPROMs) and electrically erasable programmable ROMs (EEPROMs).
Generally, the primary difference between a PROM and EPROM (or EEPROM) is that the former can be generally programmed only once, and thereafter cannot be erased. The latter can be erased through the application of ultraviolet light or electrical erasure. “Flash” memory is a type of EEPROM that can be utilized for applications requiring both nonvolatility as well as erasure.
Electronic subsystems can often include both volatile and nonvolatile memory. Typically, a volatile memory is situated within an integrated circuit that is separate and apart from an integrated circuit including a nonvolatile memory. There may be instances, however, where both volatile and nonvolatile storage elements are included in the same integrated circuit. In such instances, data targeted for volatile storage elements is generally altogether different from the data targeted for the volatile storage elements. For example, the different data sets may be for different applications.
It would be desirable to arrive at a storage device having both volatile and nonvolatile features for the same data value. For example, if data is to be temporarily held while power is present, a storage device can utilize a latch into which data can be written and thereafter read. However, if the data stored is of sufficient importance, the data could be maintained after power is removed by storing the data value into a nonvolatile storage element. Such a desired storage device could functional essentially as a latch, but also include nonvolatile storage for latched data, and thus can represent an improvement over conventional storage devices that are dedicated as either a latch or nonvolatile storage, but not both. Such a circuit can be considered a “programmable” latch circuit.
To better understand various aspects of the disclosed embodiments of the present invention, two examples of conventional programmable latches will first be described
A first conventional programmable latch is set forth in FIG. 11 in a schematic diagram and designated by the general reference character 1100. A programmable latch circuit 1100 can include a volatile latch section 1102, a read/write multiplexer section 1104, and a nonvolatile storage section 1106. A volatile latch 1102 can store a data value in response to a write operation, and output data in response to a read operation. A multiplexer section 1104 can enable data to be loaded from a nonvolatile storage (read) section 1106 into volatile section 1102, and can enable data stored (write) in volatile section 1102 to be programmed into nonvolatile storage section 1104.
In the particular example of FIG. 11, nonvolatile storage section 1106 can utilize silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile storage elements. SONOS type nonvolatile storage elements can be programmed to opposite states (e.g., conducting or non-conducting when a particular gate voltage is applied). In a load operation, the nodes of the latch can be equalized. The oppositely programmed SONOS devices can draw latch nodes to different potentials after the latch nodes are released from equalization. Thus, a data value established by the SONOS storage elements can be latched within latch section 1102.
In this way, a programmable latch can include multiple nonvolatile storage elements that store a data value, which can be latched into a volatile latch circuit.
A second conventional programmable latch is set forth in FIG. 12 in a schematic diagram and designated by the general reference character 1200. A programmable latch circuit 1200 can include a volatile latch section 1202, a multiplexer section 1204, and a nonvolatile storage section 1206. Unlike the arrangement of FIG. 11, second conventional programmable latch 1200 can be “one-time” programmable (OTP). That is, the programmable latch 1200 can utilize nonvolatile storage elements that can be programmed but once (OTP devices). In very particular example of FIG. 12, a nonvolatile storage section 1206 can include gate oxide anti-fuse (GOAF) devices 1208. In particular, GOAF devices 1208 can each be part of a three transistor (3T GOAF) cell 1210 (also referred to as a two-transistor one-cell “2T-1C” memory cell).
A drawback to the above conventional arrangements can be the area needed to implement such circuits. In particular, in order to establish complementary values at volatile latch nodes, two nonvolatile devices are utilized, and the nonvolatile devices are typically large devices. In particular, in the case of SONOS type devices, because a relatively large programming current is needed (e.g., 1 mA), relatively large device sizes are needed to supply such current to the SONOS devices. In the case of GOAF devices, a GOAF cell can occupy 30% to 40% of the programmable latch circuit.
The above drawbacks are exacerbated by the need, in some applications, for redundancy in the programmable devices. In particular, to implement full redundancy, four nonvolatile elements would have to be included, further increasing the size of the programmable latch.
In light of the above, it would be desirable to arrive at a one-time programmable latch circuit that has a smaller size than the above conventional approaches.